The use of Field Programmable Gate Arrays (FPGA) on an Application Specific Integrated Circuit (ASIC) chip and/or a system-on-a-chip to provide instruction level hardware acceleration and resource sharing is known in the art. FIG. 1 illustrates a conventional apparatus utilizing an FPGA. The apparatus can be an ASIC, a system-on-a-chip, or some other chip comprising a main processor 102, a coprocessor 104, and a local bus, such as the Processor Local Bus (PLB) 106 developed by International Business Machines Corporation™. Other local buses can also be used, such as the Advanced Micro-Controller Bus Architecture (AMBA) developed by ARM™. The coprocessor 104 comprises FPGA cells 110 and a plurality of interfaces. The interfaces include a programming interface 108, through which the FPGA 110 is programmed, a PLB interface 112, and an Auxiliary Processing Unit (APU) interface 114. The APU interface 114 enables special hardware accelerated functions to be tightly coupled to the processor 102 at the instruction flow level. For loosely coupled operations, the processor 102 communicates with the coprocessor 104 via the PLB 106. Fetched instructions inside the processor 102 are simultaneously shared with the coprocessor 104 through the APU interface. The coprocessor 104 signals the processor 102 when it sees a valid instruction, or operations code (“opcode”), for its execution unit. The coprocessor 104 then performs the requested function on operands supplied with the instruction and passes the result back to the processor 102 through the APU interface 114.
Conventionally, the logic inside the FPGA 110 is programmed by the system developer to perform specialized functions on the operands supplied by the processor 102. Multiple functions may be bit mapped inside the FPGA 110 to provide more than one operation for the coprocessor instruction. This programming is typically done during the set up of an application to be executed by the processor 102 or during chip initialization. However, if during execution of the application, the application requests a function not programmed into the FPGA 110, then the application cannot take advantage of the hardware acceleration or the resource sharing provided by the coprocessor 104, even if the requested function had existed in the library of functions available for programming the FPGA 110.
Accordingly, there exists a need for a method and apparatus for dynamically programming Field Programmable Gate Arrays (FPGA). The method and apparatus should allow FPGA's to be programmed or reprogrammed during application execution. The present invention addresses such a need.